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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">CNTNSAR, Counter-timer Non-secure Access Register</h1><p>The CNTNSAR characteristics are:</p><h2>Purpose</h2>
        <p>Provides the highest-level control of whether frames CNTBaseN and CNTEL0BaseN are accessible by Non-secure accesses.</p>
      <h2>Configuration</h2><p>It is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether CNTNSAR is implemented in the Core power domain or in the Debug power domain.
    </p>
        <p>For more information, see <span class="xref">'Power and reset domains for the system level implementation of the Generic Timer'</span>.</p>
      <h2>Attributes</h2>
        <p>CNTNSAR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="24"><a href="#fieldset_0-31_8">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_0">NS7</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_0">NS6</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_0">NS5</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_0">NS4</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_0">NS3</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_0">NS2</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_0">NS1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_0">NS0</a></td></tr></tbody></table><h4 id="fieldset_0-31_8">Bits [31:8]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-7_0">NS&lt;n&gt;, bit [n], for n = 7 to 0</h4><div class="field">
      <p>Non-secure access to frame n.</p>
    <table class="valuetable"><tr><th>NS&lt;n&gt;</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Secure access only. Behaves as <span class="arm-defined-word">RES0</span> to Non-secure accesses.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Secure and Non-secure accesses permitted.</p>
        </td></tr></table><p>This bit also determines whether, in the CNTCTLBase frame, <a href="ext-cntacrn.html">CNTACR&lt;n&gt;</a> and <a href="ext-cntvoffn.html">CNTVOFF&lt;n&gt;</a> are accessible to Non-secure accesses.</p>
<p>If frame CNTBase&lt;n&gt;:</p>
<ul>
<li>Is not implemented, then NS&lt;n&gt; is <span class="arm-defined-word">RES0</span>.
</li><li>Is not Configurable access, and is accessible only by Secure accesses, then NS&lt;n&gt; is <span class="arm-defined-word">RES0</span>.
</li><li>Is not Configurable access, and is accessible by both Secure and Non-secure accesses, then NS&lt;n&gt; is <span class="arm-defined-word">RES1</span>.
</li></ul><p>The reset behavior of this field is:</p><ul><li>On a Timer reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h2>Accessing CNTNSAR</h2>
        <p>In a system that recognizes two Security states, this register is only accessible by Secure accesses.</p>
      <h4>CNTNSAR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>Timer</td><td>CNTCTLBase</td><td><span class="hexnumber">0x004</span></td><td>CNTNSAR</td></tr></table><p>Accesses on this interface are <span class="access_level">RW</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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